Byte-operational nonvolatile semiconductor memory device

ABSTRACT

Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

[0001] This application claims the priority of Korean Patent ApplicationNo. 2003-24779, filed on Apr. 18, 2003, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein in theirentirety by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] Embodiments of the present invention relate to a nonvolatilememory (NVM) device, which is a byte-operational nonvolatilesemiconductor memory device.

[0004] 2. Description of the Related Art

[0005] Nonvolatile semiconductor memory devices are able to retain dataeven when power is not supplied. Nonvolatile semiconductor memorydevices may be classified into mask ROMs, EPROMs, and EEPROMs.Bulk-erasable EEPROMs are often called flash memories or flash EEPROMs.Each 1-bit memory cell of an EEPROM may include a pair of transistors, abit select transistor, and a memory transistor. A bit select transistoris for selecting a bit memory cell. A memory transistor is for storingdata. An EEPROM memory transistor operates utilizing a Fowler-Nordheimtunneling (F-N tunneling) mechanism when programming data or erasingdata. Bulk-erasable flash memory devices are able to erase groups ofdata stored in memory cells at one time. Bulk-erasable flash memorydevices may be classified as block-erasable, sector-erasable, orpage-erasable flash memory devices in accordance with the amount of dataerasable at one time. Each 1-bit memory cell of a bulk-erasable flashmemory device may include a single memory transistor.

[0006] Flash memory devices may be categorized as either NAND-typedevices or NOR-type devices according to the connection state of memorycells. Although a NAND-type flash memory can rapidly program and erasedata, NAND-type flash memory are not capable of random access. However,a NOR-type flash memory is capable of random access, but is slow atprogramming and erasing data. NAND-type flash memory and NOR-type flashmemory differ in operating mechanisms. During erase operations, bothNAND-type and NOR-type flash memories utilize a F-N tunnelingphenomenon. However, during program operations, while the NAND-typeflash memory operates using F-N tunneling, the NOR-type flash memoryoperates using a channel hot electron injection (CHEI) phenomenon.According to the CHEI phenomenon, a difference in electrical potentialbetween a source and a drain causes carriers to flow, while a relativelyhigh or low voltage is applied to a gate electrode. Accordingly,electrons or holes are injected into or trapped in a floating gate or aninsulating layer (e.g. a nitride layer). Since trapping of electrons orholes occurs adjacent to a source, this method is often referred to assource side injection (SSI).

[0007] Nonvolatile memory devices are used in a variety of applicationsand new applications continue to be aggressively developed. For example,nonvolatile memory devices are employed in embedded memories of memorycards. Memory cards (e.g. flash memories) are popular as storage mediain portable digital electronic devices, such as mobile phones, set-topboxes, MP3 players, digital cameras, camcorders, and PDAs.

[0008] Usefulness of nonvolatile memory devices may be increased if theyoperate to erase data one byte at a time. An example of byte-operationalnonvolatile memory devices is disclosed in U.S. patent application Ser.No. 10/022,314 (U.S. patent application Publication No. 2002/0114185A1). FIG. 1 is a description of a byte-operational nonvolatile memorydevice based on U.S. patent application Ser. No. 10/022,314. FIG. 1 is adiagram of a memory cell equivalent circuit of a byte-operationalnonvolatile semiconductor memory device. In FIG. 1, a “byte memory cell”(i.e. an 8-bit unit memory cell) is illustrated inside the dotted lines.

[0009] In FIG. 1, the byte memory cell comprises a memory cell block anda byte-operational block. The memory cell block includes 8 single-bitmemory cells. Each single-bit memory cell includes a pair of transistorsconnected in series. The pair of transistors include the memorytransistor 110 and the bit select transistor 120. The memory transistor110 has a gate electrode structure of a stacked floating gate type,which operates through F-N tunneling in both programming and erasingoperations. The byte-operational block also includes the byte selecttransistor 130. Source S of the bit select transistor 120 is connectedto drain D of the memory transistor 110. Drain D of the bit selecttransistor 120 is connected to a bit line (e.g. BL_(mo)). Each bit lineis connected in parallel to a memory transistor arrayed in another bytememory cell in the same column. Drain D of the byte select transistor130 is connected to an mth program line GSL_(m). Source S of the byteselect transistor 130 is connected to the gate G of the memorytransistor 110. Gates G of the bit select transistors 120 and the byteselect transistor 130 are commonly connected to an nth word line WL_(n).The nth word line WL_(n) is connected to both the bit select transistor120 and the byte select transistor 130 in another byte memory cellarrayed in the same row.

[0010] A nonvolatile semiconductor memory device of FIG. 1 has specificcharacteristics. For instance, since the byte select transistor 130 iscapable of selecting single-bit memory cells in groups of a byte, it isalso possible to erase data stored in the single-bit memory cells ingroups of a byte. Also, in the nonvolatile memory device of FIG. 1,voltage transmitted through the byte select transistor 130 is applied togate G of the memory transistor 110 in programming, erasing, andreading. Accordingly, voltage characteristics of source S have a greatinfluence on operating characteristics of the semiconductor memorydevice, whereas the amount of current flowing through a channel of thebyte select transistor 130 is not an important factor. Because currentis not an important factor, the byte select transistor 130 can bedisposed on the side of each byte memory cell. Accordingly, it is notnecessary for the channel width of the byte select transistor 130 tohave a large channel width.

SUMMARY OF THE INVENTION

[0011] Embodiments of the present invention relates to a nonvolatilesemiconductor memory device having a highly integrated memory celllayout, which allows data stored in groups of a byte to be erased. Anonvolatile semiconductor memory device may comprise a semiconductorsubstrate 1-byte memory transistors, and/or a byte select transistor. Anactive region and an isolation region may be defined on thesemiconductor substrate. The 1-byte memory transistors may be arrangedin one direction. Each of the memory transistors include a junctionregion and a channel region formed in the active region. The byte selecttransistor may be disposed in the active region and include a junctionregion that is directly adjacent to the junction of each of the 1-bytememory transistors.

[0012] The byte select transistor may be disposed over or under the1-byte memory transistors, perpendicular to the direction in which the1-byte memory transistors are arranged. The junction of each of the1-byte memory transistors that is directly adjacent to the junction ofthe byte select transistor may be a source region. The junction of thebyte select transistor that is directly adjacent to the junction of eachof the 1-byte memory transistors may be a drain region. Also, thejunction region and a channel region of the byte select transistor maybe disposed in an undoped native semiconductor substrate or in a dopedconductive well region. When the junction region and the channel regionof the byte select transistor are disposed in the doped conductive wellregion, the junction region and the channel region of the 1-byte memorytransistor may be disposed in the doped conductive well region. Each ofthe 1-byte memory transistors may be a device utilizing source sideinjection (SSI) during operation.

[0013] The width of a channel region of the byte select transistor maybe larger than the sum of the widths of the channel regions of the1-byte memory transistors. Also, the width of the channel region of thebyte select transistor may be equal to or larger than the sum of thewidths of the channel regions of the 1-byte memory transistors and thewidths of the isolation regions between adjacent 1-bit memorytransistors. The isolation regions may be disposed at the semiconductorsubstrate.

[0014] Each of the 1-byte memory transistors is a floating-gate-typetransistor. The memory transistors may be one of a SONOS-type transistorand a MONOS-type transistor (hereinafter, both referred to as a“SONOS-type transistor”). A gate electrode structure of a SONOS-typememory may include a first oxide layer, a nitride layer, a second oxidelayer, and/or a conductive layer. These layers are sequentially stackedand may have the same thickness. In embodiments, a gate electrodestructure of the SONOS-type transistor includes a first oxide layer anda nitride layer. The nitride layer may have a thickness smaller than afirst oxide layer. A second oxide layer and a conductive layer may bothhave the same thickness as the first oxide layer, which are sequentiallystacked.

[0015] In embodiments of the present invention, a byte-operationalnonvolatile semiconductor memory device includes a plurality of bytememory cells. Each of the byte memory cells may include a memory cellblock including 1-byte memory transistors arranged in one direction.Each of the byte memory cells may also include a byte-operational blockincluding a byte select transistor. The byte-operational block may bedisposed over or under the memory cell block and perpendicular to thedirection in which the 1-byte memory transistors are arranged.

[0016] Embodiments of the present invention relate to a device includinga plurality of bit lines. The bit lines are electrically connected torespective drain regions of the 1-byte memory transistors. The devicealso includes a plurality of global source lines, which are electricallyconnected to a source region of the byte select transistor. The devicefurther include a plurality of word lines, which are connected torespective gate lines of the 1-byte memory transistors. The device mayinclude a plurality of byte select lines, which are connected to a gateelectrode of the byte select transistor. A source region of each of the1-byte memory transistors and a drain region of the byte selecttransistor may have a shared junction region. Word lines and byte selectlines can be disposed parallel to each other. The shared junction regionmay be disposed in a doped conductive well region. A part of the sharedjunction region may be disposed in a doped conductive well region, whilethe other part of the shared junction region is disposed in a nativesemiconductor substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017]FIG. 1 is an exemplary circuit diagram of a memory cell equivalentcircuit of a byte-operational nonvolatile semiconductor memory device.

[0018]FIG. 2 is an exemplary circuit diagram of a memory cell equivalentcircuit of a byte-operational nonvolatile semiconductor memory device.

[0019]FIG. 3 is an exemplary layout of a memory cell of abyte-operational nonvolatile semiconductor memory device.

[0020]FIGS. 4A, 4B, 5A and 5B are exemplary schematic sectional viewstaken along line A-A′ of FIG. 3.

DETAILED DESCRIPTION OF THE INVENTION

[0021] The present invention will now be described more fully withreference to the accompanying drawings, in which embodiments of theinvention are shown. This invention may, however, be embodied in manydifferent forms and should not be construed as being limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure is thorough and complete and fully conveys theconcept of the invention to those skilled in the art. In the drawings,the thicknesses of layers may be exaggerated for clarity, and the samereference numerals are used to denote the same elements throughout thedrawings.

[0022]FIG. 2 is an exemplary circuit diagram of a byte memory cell of abyte-operational non-volatile semiconductor memory device. In FIG. 2, abyte memory cell includes the local source line LSL, the 1-byte memorytransistors 210, and the byte select transistor 230. The 1-byte memorytransistors 210 and the byte select transistor 230 are connected to thelocal source line LSL. The byte memory cell may be connected to adjacentbyte memory cells through the global source lines GSL, the bit lines BL,the byte select lines BSL, and/or the word lines WL. In FIG. 2, the bytememory cell is illustrated with a dotted line.

[0023] A byte memory cell may include a memory cell block including the1-byte memory transistors 210, the byte-operational block (including thelocal source line LSL_(nm)), and the byte select transistor 230. The1-byte memory transistors 210 may be connected parallel to the localsource line LSL_(nm). Also, the local source line LSL_(nm) may beconnected to the byte select transistor 230. The local source lineLSL_(nm) may also be connected to the sources S or the drains D of eachof the 1-byte memory transistors 210 and the byte select transistor 230.For example, the source S of each of the 1-byte memory transistors 210and the drain D of the byte select transistor 230 may be respectivelyconnected to the local source line LSL_(nm).

[0024] The source S or the drain D of byte select transistor 230 isconnected to the GSL_(m). The gate G of the byte select transistor 230may be connected to the byte select line BSL_(n). The source S or thedrain D of each of the 1-byte memory transistors 210 may be connected tothe mth bit line (i.e. one of BL_(m0) through BL_(m7)). The gate G ofmemory transistor 210 may be connected to the nth word line WL_(n) .

[0025] The exemplary equivalent circuit illustrated in FIG. 2 may becharacterized by the drain D of the byte select transistor 230 beingconnected to the source S of each of the 1-byte memory transistors 210.The drain D of the byte select transistor 230 is connected to the sourceS of each of the 1-byte memory transistors 210 in parallel through thelocal source line LSL_(nm). Current flowing through a channel of thebyte select transistor 230 flows into the bit lines BL through thesources S of the memory transistors 210.

[0026] Each 1-byte memory transistor 210 may be a device that operatesthrough F-N tunnelling or source side injection (SSI). For each 1-bytememory transistor 210 operating through SSI, a sufficient difference inelectrical potential is required between the source S and the drain D.Also, a sufficient amount of hot electrons or hot holes should begenerated in a channel of each memory transistor 210. Accordingly, asufficient amount of current should flow through the channel of eachmemory transistor 210.

[0027] Current flowing through the single byte select transistor 230 maybe supplied to each 1-byte memory transistor 210. Accordingly, currentdriving capacity of the byte select transistor 230 is relevant forprogramming, erasing, and reading operations in the memory transistors210. In other words, the byte select transistor 230 should supply the1-byte memory transistors 210 with a current required for programmingall eight transistors associated with 1-byte of data at the same time. Ahigh voltage should be applied to the source S of each 1-byte memorytransistor 210 through the byte select transistor 230 in order to causea sufficient amount of hot electrons or hot holes to flow into each1-byte memory transistor 210. For example, during program or eraseoperations, a high voltage applied through the global source lineGSL_(m) may need to be transmitted to the source S of each 1-byte memorytransistor 210. In embodiments, threshold voltage V_(th) of byte selecttransistor 230 is as low as possible. For example, the threshold voltageV_(th) may be 0V or lower in order to minimize lowering of electricalpotential through the byte select transistor 230.

[0028]FIG. 3 is an exemplary diagram of a byte-operational non-volatilesemiconductor memory device according to the exemplary equivalentcircuit of FIG. 2. FIG. 3 shows a layout of adjacent two-byte memorycells, according to embodiments of the present invention. A byte memorycell comprises the 1-byte memory transistors 210 and the byte selecttransistors 230. The byte memory cell is connected to adjacent bytememory cells through mth bit lines BL_(m0) through BL_(m7), the mthglobal source line GSL_(m), the nth word line WL_(n), and the nth byteselect line BS_(n).

[0029] The 1-byte memory transistors 210 are arranged in one direction(e.g. an x-axis direction) in an active region of a semiconductorsubstrate. A memory block comprises the 1-byte memory transistors 210and a gate line (which extends to be a part of the nth word lineWL_(n)), which connects the gate electrodes of the 1-byte memorytransistors 210. The byte select transistor 230 may be located over orunder the memory transistors 210 in a direction (e.g. a y-axisdirection) perpendicular to the arranged direction of the memorytransistors 210. A byte-operational block includes the byte selecttransistor 230. Memory cell block and the byte select block may bearranged parallel to each other.

[0030] Gate electrodes of byte memory cells are connected in the x-axisdirection to constitute word line WL_(n). Gate electrodes of the byteselect transistors 230 of the byte memory cell are connected in thex-axis direction to form the byte select line BSL_(n). Meanwhile, thebit lines BL_(m0) through BL_(m7) and the global source line GSL_(m) maybe arranged in a direction perpendicular to the word line WL_(n) (i.e.,in the y-axis direction). A junction (a drain) of each 1-byte memorytransistor 210 is electrically connected to the bit lines BL_(m0)through BL_(m7) through a contact. This contact may be a shared contact,which is connected to a drain of a memory transistor of an adjacent bytememory cell.

[0031] The 1-byte memory transistors 210 may be arranged in the x-axisdirection. The byte select transistor 230 may be located over or underthe memory transistors 210 in the y-axis direction. In other words, ajunction of each 1-byte memory transistor 210 and a junction of the byteselect transistor 230 may be formed in the same active region anddirectly adjacent to each other. For example, the junction of each1-byte memory transistor 210 and the junction of the byte selecttransistor 230 may constitute a shared junction. In other words, thesource of each 1-byte memory transistor 210 and drain of the byte selecttransistor 230 may form a shared junction.

[0032] Since there is a shared junction and the 1-byte memorytransistors and the byte select transistor are arranged adjacently, thechannel width of byte select transistor 230 can be sufficientlyincreased. In FIG. 3, the channel width of the byte select transistor230 is larger than the sum of the channel widths of the eight 1-bytememory transistors 210. In addition, the channel width of the byteselect transistor 230 is equal to or larger than the sum of the widthsof isolation regions. Each isolation region is located between every twomemory transistors 210 and the widths of the 1-byte memory transistors230. The exemplary layout illustrated FIG. 3 is adequate for asemiconductor device of which programming, erasing, and readingcharacteristics depend largely on current driving capacity of a byteselect transistor. This layout enable manufacture of a byte selecttransistor with a sufficient channel width. Because the channel width ofthe byte select transistor is sufficient, the required current fordriving all of the 1-byte memory transistors can be supplied through asingle byte select transistor. The memory cell layout according toembodiments of the present invention can contribute greatly to highintegration of semiconductor memory device, compared to a layout inwhich a byte select transistor is located on the side of 1-byte memorytransistors.

[0033] There are complications that arise if a byte select transistor islocated on either the right side or left side of 1-byte memorytransistors. One complication that arises is that if the byte selecttransistor is located on either side of the memory transistors, thenintegration on a chip may be compromised. Further, if the byte selecttransistor is located on either side of a memory transistors, there maybe variance in resistance between respective memory transistors.Accordingly, in embodiments of the present invention, it is advantageousfor the byte select transistor 230 to be located either above or belowthe memory transistors 210. When the byte select transistor 230 is aboveor below the memory transistors 210, for each of the memory transistors210, there is a uniform distance to the byte select transistor 230.Accordingly, there may be nominal variance in resistance at each of thememory transistors 210. Additionally, if the byte select transistor 230is located above or below the memory transistors 210, then each bytememory cell can be easily integrated on a chip.

[0034] Exemplary structures of memory transistors and byte selecttransistors, in accordance with embodiments of the present invention,are illustrated in FIGS. 4A, 4B, 5A, and 5B. FIGS. 4A, 4B, 5A, and 5Bare schematic sectional views taken along line A-A′ of FIG. 3. Asdiscussed above, each memory transistor 210 is a device that may operateaccording to either F-N tunneling or source side injection (SSI).However, the illustrations of FIGS. 3, 4A, 5A, and 5B illustrate adevice operating according to SSI during programming and/or erasing.However, one of ordinary skill in the art would appreciate that thestructures illustrated in FIGS. 3, 4A, 5A, and 5B can be modified tooperate according to F-N tunneling during programming and/or erasing.Memory transistor that operates according to SSI, may have a gateelectrode structure of a stacked floating gate type,silicon-oxide-nitride-oxide-silicon (SONOS) type, ormetal-oxide-nitride-oxide-silicon (MONOS) type.

[0035] The memory transistor illustrated in FIGS. 4A and 4B have aSONOS-type or MONOS-type gate electrode structure. Hereinafter, bothSONOS-type and MONOS-type memory transistors are referred to as a“SONOS-type memory transistors”. A SONOS-type memory transistor mayinclude a first oxide layer, a nitride layer, a second oxide layer, anda conductive layer stacked sequentially. These layers may have the samewidth as a channel region of the memory transistor. The exemplarystructures illustrated in FIGS. 5A and 5B are similar to the exemplarystructures illustrated in FIGS. 4A and 4B. However, in the exemplarystructures of FIGS. 5A and 5B, the width of the nitride layer may besmaller than the channel region of the transistor. In the exemplarystructures of FIGS. 5A and 5B, since electrons or holes are injectedinto and move toward the vicinity of a source of a SONOS-type memorytransistor, the nitride layer is typically disposed adjacent to thesource of the transistor. In FIGS. 4A, 4B, 5A, and 5B, the lefttransistor is a memory transistor and the right transistor is a byteselect transistor. The memory transistor is illustrated as a SONOS-typememory transistor. However, one of ordinary skill in the art willappreciate that embodiments of the present invention are applicable todifferent types of memory transistors other than SONOS-type memorytransistors.

[0036] In FIGS. 4A and 4B, each of the widths of the first oxide layer331, the nitride layer 332 a, the second oxide layer 333, and thepolysilicon layer 334 constituting a SONOS memory transistor aresubstantially equal to the channel width of the transistor. Inembodiments where MONOS-type memory transistor is used, the polysiliconlayer 334 may be replaced by a metal layer. However, the other materialsand structures may otherwise be essentially the same as a SONOS-typememory transistor. In the SONOS-type memory transistor illustrated inFIGS. 5A and 5B, the width of nitride layer 332 b may be smaller thanthe channel width of the transistor. However, each of the widths of thefirst oxide layer 331, the second oxide layer 333, and the polysiliconlayer 334 may be substantially equal to the channel width. In FIGS. 5Aand 5B, the nitride layer 332 b may be disposed on one side of theSONOS-type memory transistor. In the structures illustrated in FIGS. 4A,4B, 5A, and 5B, irrespective of the types of the gate electrodestructures of the memory transistors, the byte select transistor mayhave a gate electrode structure where the gate oxide layer 336 and thegate conductive layer 338 are stacked.

[0037] Table 1 illustrates examples of voltages applied to elements ofbyte-operational nonvolatile semiconductor memory devices illustrated inFIGS. 4A, 4B, 5A, and 5B during program, erase, and read operations.V_(gs1) is a voltage applied to a global source line. V_(bs1) is avoltage applied to a byte select line. V_(w1) is a voltage applied to aword line. V_(b1) is a voltage applied to a bit line. V_(b) is a bulkvoltage (i.e. a voltage applied to a silicon substrate). TABLE 1 V_(gs1)V_(bs1) V_(w1) V_(b1) V_(b) Program 6 V   6 V 5.5 V   1 V GND Erase 6 V  6 V  −5 V Floating GND Read GND 1.8 V 2.5 V or 3.3 V 0.5 V GND

[0038] In FIG. 4A, a gate electrode structure of a memory transistor anda gate electrode structure of a byte select transistor are disposed onthe semiconductor substrate 300. A channel of the memory transistor isdisposed in a first-conductivity-type well region (e.g. the p-type wellregion 310 a). In embodiments, a channel of the byte select transistormay be disposed in a native semiconductor substrate.

[0039] The source/drain regions 322 and 324 are disposed in thesemiconductor substrate 300 on both sides of the gate electrodestructure of the memory transistor. The source/drain region 320 and thesource/drain region 322 are disposed in the semiconductor substrate 300on both sides of the gate electrode structure of the byte selecttransistor. In embodiments, the source/drain regions 320, 322, and 324may be formed by implanting n-type impurity ions into the semiconductorsubstrate 300.

[0040] In FIGS. 4A and 5A, according to embodiments, the channel of thememory transistor may be disposed in the p-type well region 310 a, whilethe channel of the byte select transistor is disposed in the nativesubstrate. In other words, the channel of the byte select transistor isnot in the well region 310 a. If the channel of the byte selecttransistor is disposed in the native substrate, a threshold voltage ofthe byte select transistor may be relatively low (e.g. 0 V or lower). Ifthe threshold voltage is 0 V or lower, lowering of electrical potentialin a byte select transistor (i.e. a substrate effect) can be minimized.Thus, voltage transmitted to the source/drain region 322 of the memorytransistor through the byte select transistor is not lowered.Accordingly, the byte select transistor can secure a sufficient currentdriving capacity.

[0041] In the exemplary semiconductor memory devices illustrated inFIGS. 4B and 5B, according to embodiments of the present invention, thechannel of the byte select transistor is disposed in afirst-conductivity-type well region (e.g. a p-type well region 310 b).Accordingly, the exemplary semiconductor memory devices of FIGS. 4B and5B have a byte select transistor threshold voltage higher than theexemplary semiconductor devices illustrated in FIGS. 4A and 5A. However,in the embodiments illustrated in FIGS. 4B and 5B, the distance betweenthe gate electrode structures of the byte select transistor and thememory transistor may be less than the embodiment illustrated in FIGS.4A and 5A. This compactness may be due to both the byte selecttransistor and the memory transistor being formed in the same p-typewell region 310. Accordingly, since the area occupied by a unit bytememory cell can decrease due to reduced distance between the two gateelectrode structures, integration density can be increased.

[0042] A byte-operational nonvolatile semiconductor memory device mayhave a memory cell equivalent circuit and a memory cell layout that canbe applied to electronic devices requiring byte-operational programmingand erasing. Nonvolatile memory devices, in accordance with embodimentsof the present invention, may be advantageous for memory cards requiringbyte-operational erasing. Byte-operational nonvolatile semiconductormemory devices, according to embodiments of the present invention,improve current driving capacity of the byte select transistor. Thisimproved current driving capacity may improve performance of a memorydevice.

[0043] In a memory cell layout of the byte-operational nonvolatilesemiconductor memory device, according to embodiments of the presentinvention, the byte select transistor may be disposed over or under1-byte memory transistors, arranged in one direction perpendicular tothe arranged direction of the 1-byte memory transistors. A semiconductormemory device, according to embodiments of the present invention, mayenable byte operations, may allow a sufficient amount of current to flowthrough the byte select transistor, and may prevent lowering of voltagein the byte select transistor due to substrate effect. Further, sincethe area occupied by a unit byte memory cell may be reduced, integrationdensity can be increased and sufficient channel width can be secured inspite of high integration density.

What is claimed is:
 1. A nonvolatile semiconductor memory devicecomprising: a semiconductor substrate comprising an active region and anisolation region; 1-byte memory transistors arranged in a firstdirection, wherein each of the 1-byte memory transistors includes ajunction region and a channel region formed in the active region of thesemiconductor substrate; and a byte select transistor disposed in theactive region, wherein the byte select transistor includes a junctionregion that is directly adjacent to the junction of each of the 1-bytememory transistors.
 2. The device of claim 1, wherein the byte selecttransistor is disposed over or under the 1-byte memory transistorsperpendicular to the arranged direction of the 1-byte memorytransistors.
 3. The device of claim 1, wherein the junction of each ofthe 1-byte memory transistors that is directly adjacent to the junctionof the byte select transistor is a source region.
 4. The device of claim1, wherein the junction of the byte select transistor that is directlyadjacent to the junction of each of the 1-byte memory transistors is adrain region.
 5. The device of claim 1, wherein the junction region anda channel region of the byte select transistor are disposed in anundoped native semiconductor substrate.
 6. The device of claim 1,wherein the junction region and a channel region of the byte selecttransistor are disposed in a doped conductive well region.
 7. The deviceof claim 6, wherein the junction region and a channel region of each ofthe 1-byte memory transistors are disposed in the doped conductive wellregion.
 8. The device of claim 1, wherein each of the 1-byte memorytransistors is a device operating according to source side injection. 9.The device of claim 1, wherein the width of a channel region of the byteselect transistor is larger than the sum of the widths of channelregions of the 1-byte memory transistors.
 10. The device of claim 9,wherein the width of the channel region of the byte select transistor isequal to or larger than the sum of the widths of the channel regions ofthe 1-byte memory transistors and the widths of the isolation regionsbetween adjacent 1-byte memory transistors.
 11. The device of claim 1,wherein each of the 1-byte memory transistors is a floating-gate-typetransistor.
 12. The device of claim 1, wherein each of the 1-byte memorytransistors is a silicon-oxide-nitride-oxide-silicon-type transistor ora metal-oxide-nitride-oxide-silicon-type transistor.
 13. The device ofclaim 12, wherein a gate electrode structure of thesilicon-oxide-nitride-oxide-silicon-type transistor or themetal-oxide-nitride-oxide-silicon-type transistor includes a first oxidelayer, a nitride layer, a second oxide layer, and a conductive layer,which are sequentially stacked and have substantially the same width.14. The device of claim 12, wherein: a gate electrode structure of thesilicon-oxide-nitride-oxide-silicon-type transistor or themetal-oxide-nitride-oxide-silicon-type transistor includes a first oxidelayer, a nitride layer, a second oxide layer, and a conductive layerstacked sequentially; the first oxide layer, the second oxide layer, andthe conductive layer have substantially the same width; and the nitridelayer has a width smaller than the first oxide layer, the second oxidelayer, and the conductive layer.
 15. A byte-operational nonvolatilesemiconductor memory device including a plurality of byte memory cells,each of which comprises: a memory cell block including 1-byte memorytransistors arranged in one direction; and a byte-operational blockincluding a byte select transistor and disposed over or under the memorycell block and perpendicular to the direction in which the 1-byte memorytransistors are arranged.
 16. The device of claim 15, furthercomprising: a plurality of bit lines, which are electrically connectedto drain regions of the 1-byte memory transistors, respectively; aplurality of global source lines, which are electrically connected to asource region of the byte select transistor; a plurality of word lines,which are connected to gate lines of the 1-byte memory transistors,respectively; and a plurality of byte select lines, which are connectedto a gate electrode of the byte select transistor, wherein a sourceregion of each of the 1-byte memory transistors and a drain region ofthe byte select transistor constitute a shared junction region.
 17. Thedevice of claim 16, wherein the word lines and the byte select lines aredisposed parallel to each other.
 18. The device of claim 16, wherein theshared junction region is disposed in a doped conductive well region.19. The device of claim 16, wherein a part of the shared junction regionis disposed in a doped conductive well region and the other part of theshared junction region is disposed in a native semiconductor substrate.20. The device of claim 15, wherein the source region, the drain region,and a channel region of the byte select transistor are disposed in anundoped native semiconductor substrate.
 21. The device of claim 15,wherein the source region, the drain region, and a channel region of thebyte select transistor are disposed in a doped conductive well region.22. The device of claim 21, wherein the source region, the drain region,and a channel region of each of the 1-byte memory transistors aredisposed in the doped conductive well region.
 23. The device of claim15, wherein each of the 1-byte memory transistors is a device operatingthrough source side injection.
 24. The device of claim 15, wherein thewidth of a channel region of the byte select transistor is larger thanthe sum of the widths of channel regions of the 1-byte memorytransistors.
 25. The device of claim 15, wherein each of the 1-bytememory transistors is a floating-gate-type transistor.
 26. The device ofclaim 15, wherein each of the 1-byte memory transistors is asilicon-oxide-nitride-oxide-silicon-type transistor or ametal-oxide-nitride-oxide-silicon-type memory transistor.
 27. The deviceof claim 26, wherein a gate electrode structure of thesilicon-oxide-nitride-oxide-silicon-type transistor or themetal-oxide-nitride-oxide-silicon-type memory transistor includes afirst oxide layer, a nitride layer, a second oxide layer, and aconductive layer, which are sequentially stacked and have the samewidth.
 28. The device of claim 26, wherein: a gate electrode structureof the silicon-oxide-nitride-oxide-silicon-type transistor or themetal-oxide-nitride-oxide-silicon-type memory transistor includes afirst oxide layer, a nitride layer, a second oxide layer, and aconductive layer, which are sequentially stacked; the first oxide layer,the second oxide layer, and the conductive layer have substantially thesame width; and the nitride layer has a width less than the width of thefirst oxide layer, the second oxide layer, and the conductive layer. 29.An apparatus comprising a memory cell, wherein the memory cellcomprises: a plurality of first transistors configured to store data;and a second transistor configured to activate the plurality of firsttransistors at the same time, wherein: a source or a drain of each ofthe plurality of first transistors is connected to a source or a drainof the second transistor; the resistance of each connection between eachof the plurality of first transistors and the second transistor issubstantially the same.
 30. The apparatus of claim 29, wherein thelength of each connection between each of the plurality of firsttransistors and the second transistor is substantially the same.
 31. Theapparatus of claim 30, wherein the length of each connection betweeneach of the plurality of first transistors and the second transistor isminimized.
 32. The apparatus of claim 29, wherein: the plurality offirst transistors are arranged parallel to each other in a row; achannel of the second transistor is substantially parallel to eachchannel of each of the plurality of first transistors.
 33. The apparatusof claim 32, wherein the channel width of the second transistor extendsapproximately the length of the row of the plurality of firsttransistors.
 34. The apparatus of claim 33, wherein each connectionbetween each of the plurality of first transistors and the secondtransistor is at a different point along the source or the drain of thesecond transistor.
 35. The apparatus of claim 29, wherein the apparatusis comprised in a NOR-type flash memory device utilizing source sideinjection during operation.
 36. The apparatus of claim 29, wherein theplurality of first transistors comprise at least three transistors. 37.The apparatus of claim 36, wherein the plurality of first transistorscomprise eight transistors.